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EV GroupBayern, DEVerification Engineer – Digital ASIC / System on Chip (SoC) Design
Fraunhofer-Institut für Integrierte Schaltungen IISErlangen, Bayern, Deutschland- Quick Apply
Verification Engineer – Digital ASIC / System on Chip (SoC) Design at Fraunhofer-Institut für Integrierte Schaltungen IIS | softgarden
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Verification Engineer – Digital ASIC / System on Chip (SoC) Design
Full or Part Time
Hybrid
Am Wolfsmantel 33, 91058, Erlangen
Without Professional Experience
2 / 14 / 25
The Fraunhofer-Gesellschaft ( www.fraunhofer.com ) currently operates 76 institutes and research institutions throughout Germany and is the world’s leading applied research organization. Around 30 000 employees work with an annual research budget of 2.9 billion euros.
We bring chip design back to Europe!
For a technologically more independent Europe, we aim to develop Fraunhofer IIS into a European IC Design Center for trusted and energy-efficient high-speed ICs by 2025. As a leading competence center for digital chip design, we deliver essential cutting-edge technologies in the areas of exascale high-performance computing and trusted electronics. In addition, we offer sophisticated digital design services based on RISC-V. Our target customers are design houses, semiconductor manufacturers, SMEs, and system integrators. Potential applications are areas such as high-speed data processing, blockchain or cybersecurity. Today, our »Integrated Digital Systems« business unit develops digital circuits in CMOS technologies as System on Chip, ASIC or IP.
What you will do
As a hardware developer, you will specify, design and verify hardware components of complex ASICs and SoCs with embedded microprocessors (RISC-V) in System-Verilog. You will also work with constrained random coverage-driven testbenches using the UVM Framework. In detail, this means :
- By performing feature extraction from register-transfer level (RTL) specifications, you will produce verification plans that are supported by metrics obtained from simulation.
- You will also generate, maintain, and expand test benches based on the UVM framework.
- Using your profound knowledge, you will also contribute to tasks like test development and debugging.
- When working with a device under test (DUT), you will develop precise coverage models.
- By writing SVA assertions and scoreboard checkers, you will ensure the correct operation of the DUT.
- Last but not least, you will prepare, execute and analyze regression runs.
What you bring to the table
What you can expect
Fraunhofer is not only the largest organization for applied research (application-oriented research organisation) in Europe, but also a top-rated employer. How so?
The weekly working time is 39 hours. The position is initially limited to 2 years with the aim to extend it subsequently.
We value and promote the diversity of our employees' skills and therefore welcome all applications – regardless of age, gender, nationality, ethnic and social origin, religion, worldview, disability, sexual orientation and identity. Severely disabled persons are given preference in the event of equal suitability. Appointment, remuneration, and social security benefits are based on the German public-sector collective wage agreement (TVöD). Additionally, Fraunhofer may grant performance-based variable remuneration components.
With its focus on developing key technologies that are vital for the future and enabling the commercial utilization of this work by business and industry, Fraunhofer plays a central role in the innovation process. As a pioneer and catalyst for groundbreaking developments and scientific excellence, Fraunhofer helps to shape society both in the present and in the future.
Interested?
Apply online now (Motivation letter, CV, certificates). We look forward to getting to know you!
Questions about this position will be answered by Simon Zimmermann.
Fraunhofer Institute for Integrated Circuits IIS
www.iis.fraunhofer.de
Apply Online
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