Join a leading technology team focused on advancing high-speed memory interface designs.
You’ll contribute to the development and verification of critical analog and mixed-signal circuits that enable reliable and high-performance DDR memory interfaces across a range of applications.
What You’ll Do :
- Lead the design and verification of high-speed DDR PHY interfaces, including key components such as transmitters, receivers, delay-locked loops (DLL), on-die termination (ODT), and clock duty cycle circuits.
- Work collaboratively with layout engineers to provide design guidelines and ensure manufacturability and robustness.
- Perform post-layout simulations to validate timing, signal integrity, jitter, and crosstalk using standard industry tools.
- Ensure designs meet industry standards for DDR interfaces through thorough testing and verification.
- Utilize advanced design and simulation software to support the full design cycle of analog and mixed-signal blocks.
- Own the design process from concept through to verification and hardware implementation for projects of typical duration around six months.
What You’ll Need :
Degree in Electrical Engineering, Electronics, or a related discipline.Significant experience (5+ years) in designing and verifying DDR PHY interfaces.Expertise in analog and mixed-signal design, including DLLs, ODTs, and transmitter / receiver circuits.Proficiency with industry-standard design and simulation tools (e.g., Cadence, SPICE).Solid understanding of DDR interface standards and experience ensuring design compliance.Strong collaboration skills for working with physical design / layout teams.Proven ability to conduct post-layout parasitic extraction and signal integrity verification.