Senior Verification Engineer

ROLE : Senior Formal Verification Engineer

LOCATION : Mannheim, Germany (Hybrid) or Villach, Austria (Hybrid)

SALARY : Negotiable

DURATION : Permanent

About the Role :

We’re seeking an experienced Senior Functional Verification Engineer to join a high-performing team developing and verifying cutting-edge on-chip network (NoC) solutions.

This is an excellent opportunity to contribute to complex, high-impact projects where design quality, timely delivery, and innovation are at the forefront.

Key Responsibilities :

• Develop and maintain UVM SystemVerilog verification environments for NoC IPs.
• Define and execute comprehensive verification plans aligned with design and product requirements.
• Design, implement, and continuously enhance testbenches and verification components .
• Debug and analyze functional and performance issues , ensuring robust, high-quality designs.
• Drive coverage closure and monitor daily regression results .
• Collaborate closely with digital design and cross-functional teams to achieve successful, on-time product releases.

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