Verification Engineer
Working as a Senior Digital Verification Engineer, you will :
- Define test bench infrastructure using SystemVerilog, UVM and Formal.
- Responsible for complete digital level verification.
- Modeling of analog functions in SystemVerilog.
- Responsible for complete chip level verification of mixed signal IC.
- Work closely with design team to architect a new design verification environment and produce high quality verification closure.
- Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
What We Are Looking For?
- 3+ years of experience in ASIC / IC verification or design.
- Experience in UVM based verification flow.
- Good understanding of OOP concepts
- Familiar with scripting language like Makefile, Perl, Tcl or Python.
- Experience in SimVision or Verdi debug skills.
- Experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking) is a plus.
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